SOF Data Properties Dialog Box (Convert Programming File) Compression and Encryption Settings (Convert Programming File) Bitstream Co-Signing Security Settings (Programming File Generator) Add Partition Dialog Box (Programming File Generator) Output Files Tab Settings (Programming File Generator) Input Files Tab Settings (Programming File Generator) Generic Flash Programmer Settings Reference Termination Flow Template ( Intel Arria 10 and Intel Cyclone 10 GX) Verify/Blank-Check/Examine Flow Template ( Intel Arria 10 and Intel Cyclone 10 GX) Erase Flow Template ( Intel Arria 10 and Intel Cyclone 10 GX) Program Flow Template ( Intel Arria 10 and Intel Cyclone 10 GX) Initialization Flow Templates ( Intel Arria 10 and Intel Cyclone 10 GX) Generic Flash Programmer Flow Templates ( Intel Arria 10 and Intel Cyclone 10 GX) Termination Flow Template ( Intel Stratix 10 Devices) Verify/Blank-Check/Examine Flow Template ( Intel Stratix 10 Devices) Erase Flow Template ( Intel Stratix 10 Devices) Program Flow Template ( Intel Stratix 10 Devices) Initialization Flow Template ( Intel Stratix 10 Devices) Generic Flash Programmer Flow Templates ( Intel Stratix 10 devices)
Enabling Bitstream Encryption or Compression for Intel Arria 10 and Intel Cyclone 10 GX Devices Step 2: Generate Secondary Programming Files (Convert Programming Files) Step 1: Generate Primary Device Programming Files Generic Flash Programming (Convert Programming File Dialog Box) Defining a New Flash Memory Configuration Device Enabling Bitstream Encryption (Programming File Generator) Enabling Bitstream Authentication (Programming File Generator) Step 2: Generate Secondary Programming Files (Programming File Generator) Step 1: Generate Primary Device Programming File Generic Flash Programming (Programming File Generator) Supported Devices and Configuration Methods
QUAD SPI PROGRAMMER PRO
Generic Flash Programmer User Guide Intel Quartus Prime Pro Edition Generic Flash Programmer User Guide: Intel Quartus Prime Pro Edition.
QUAD SPI PROGRAMMER HOW TO
For further information regarding the Open Flashloader and how to use the JLinkDevices.xml file, please refer to the J-Link User Manual (UM08001), chapter 10 Open Flashloader. In general this change effects the pin / port initialization, only. If there is no example flash algorithm for your port / pin configuration available, the flash algorithm needs to be slightly modified. This allows customer to easily exchange the used flashloader by replacing the flashloader file referenced by the JLinkDevices.xml.
The flash algorithms are based on the Open Flashloader concept. Information about what needs to be done if a different pin configuration is used can be found below (see Customized Solution Required). If you chose the same pin layout as used on the evaluation board, the flash algorithms can be used out-of-the-box.
Thus, for each possible pin / port configuration a slightly different flash algorithm is required, even if the same SPI flash and the same CPU is used.įor CPUs, which allow to use different port / pin configurations, we create 1-2 example flash algorithms, based on the pin configuration of the evaluation board. Some CPUs allow to use different port / pin configurations for the connection of the SPI flash. This allows the J-Link DLL to support flash programming through the Quad-SPI interface of the CPU. More and more CPUs include an so called SPIFI memory controller which allows memory mapped read accesses to any SPI flash, connected to the Quad-SPI interface of the CPU.